Asynchronous Systems on Programmable Logic

This paper describes a general methodology to prototype asynchronous systems onto LUT based FPGAs. The main objective is to offer to the system designers the powerfulness of standard synchronous FPGAs to prototype their asynchronous circuits or mixed synchronous/asynchronous circuits. To avoid hazard in FPGAs, the appearance of hazard in configurable logic cells is analyzed and a technique based on a Muller gate library is proposed. Moreover, the method is extended to the arbiter and synchronizer design. They are necessary to prototype complex systems with multi-clock domains and asynchronous logic. In order to illustrate this innovating methodology for fast and easy prototyping of asynchronous systems, a sample system including an asynchronous Network-on-Chips (ANoCs) is presented. The system is implemented on a multi-clock FPGA and includes synchronous standard IP cores and asynchronous modules connected through an asynchronous 5x5 crossbar.